In a conventional storage system, such as a nonvolatile storage system, data can be stored in accordance with a predetermined error correction coding scheme, such as a low-density parity-check (LDPC) coding scheme. Such a nonvolatile storage system can include a plurality of nonvolatile memory (NVM) devices, each NVM device containing a multitude of NVM storage elements or cells for storing encoded data in the form of LDPC codewords. When reading LDPC codewords from such NVM devices, one or more reference threshold voltage levels can be established between a plurality of programming states of each NVM cell, and a threshold voltage level of the NVM cell can be compared to the respective reference threshold voltage levels to determine the actual programming state of the NVM cell.
In a typical mode of operation, in order to read a desired LDPC codeword from a selected NVM device, a hard bit read operation can be performed, in which the LDPC codeword is read from the selected NVM device as so-called “hard data” (i.e., the logical high and low bit levels in the LDPC codeword are taken as a “1” and “0”, respectively). Further, a soft bit read operation can be performed, in which the LDPC codeword is read from the selected NVM device as so-called “soft data” (i.e., the logical high and low bit levels in the LDPC codeword are taken as “1” and “0”, respectively, and probability information is provided indicating the likelihood that a respective bit in the LDPC codeword is a “1” or “0”). The LDPC codeword read from the selected NVM device can then undergo error correction decoding to determine whether or not the LDPC codeword is valid. If the decoded LDPC codeword is found to be invalid or “faulty” (e.g., there may have been an error correction coding/decoding failure), then additional LDPC codewords can be read from the other NVM devices, and XOR data recovery can be performed using the additional LDPC codewords in an attempt to recover the desired LDPC codeword.
Such a detection of a faulty LDPC codeword may indicate, among other things, that a physical memory page on the selected NVM device is being affected by an underlying hardware defect (e.g., an open or short circuit), or that the selected NVM device has an intrinsically high residual bit error rate (RBER). In any case, it would be desirable to have a mechanism for managing defects in nonvolatile storage systems that can be used to avoid an inadvertent loss of data, while maintaining as much useful memory in the nonvolatile storage systems as possible.